DFT Team Leader (W/M)

Job function SCALINX’s Design Team is looking for a dynamic and experienced DFT Team Leader who will contribute to define, implement and follow-up on the DFT activities and delivery. The candidate will ensure the management, animation and development of a Design For Test team.

Work description 

• Be responsible for all Design For Test activities for all circuits in close collaboration with the R&D Development Director.
• Contribute to the development of the technical expertise of the Design For Test team(s) in close collaboration with the technical and development director.
• Be responsible for the methodology of the design flow (insertion of the DFT, Static Timing Analysis, generation of test vectors, and validation)
• DRC checks by SPYGLASS in RTL. DFT design constraints creation
• Responsible for analyzing DFT metrics and the proposed solution in order to achieve objectives in terms of yield, test-coverage goals, and test time on wafer/package and in operation.
• Work in close collaboration with the FE design and Back-End Digital teams to guarantee DFT insertion with minimal impact on circuit PPAs
• Responsible for static timing analysis for all test logic at the physical partition level and top level
• Work with test engineers to provide and validate test patterns on ATE
• Define the strategy for testing analog parts of the design
• Coordination of the production launch of several circuits per year
• Ensure the technical objectives and quality of the product as well as the development process. Ensure work on the product is properly documented
• Lead, organize, and participate in Design For Test reviews
• Report progress and problems to the project team and the development director

Qualification and Experience 

• As a leader in the DFT area, you will have strong visibility internally and externally and will be responsible for defining the DFT architecture and its implementation on complex SoCs.
• More than 10+ years of experience in DFT
• Experience in defining architecture and planning DFT stages on complex circuits (more than 30M instances)
• Experience with Scan/EDT/SSN, Logic BIST, MBIST, ATPG, and Boundary Scan on complex circuits (more than 30M instances)
• Experience with scripting languages like Pearl, TCL, or Python
• Experience with logic synthesis and static timing analysis
• Experience with the DFT flow, ideally with Tessent tools
• Good vision of design concepts, simulations, and physical implementation on the quality of the final product
• Good written and oral communication in English combined with a leader/unifier temperament and a positive & proactive attitude

How to apply 

If you have a passion for IC design and the ambition to create outstanding products, it will be a great pleasure to receive your resume at [email protected]

SCALINX is committed to diversity & equity, we aim to improve disability inclusion within our workforce.